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M.2 Pinning

This chapter presents the pinning used for the M.2 modules from Embedded Artists. It is essentially M.2 Key-E compliant with enhancements to support additional debug signals and 3.3V VDDIO override. The pin assignment for specific control and debug signals has been jointly defined by Embedded Artists, Murata, NXP and Infineon/Cypress.

The Wi-Fi interface is either SDIO, PCIe or USB, depending on the used Murata module.

The Bluetooth interface is UART (and PCM for audio) or USB, depending on the used Murata module.

Optionally, an NFC interface can also be supported via I2C, USB or UART.

Note that the information in the table below is not a complete copy of the M.2 specification. For specific details see the official M.2 specification (PCI Express M.2 Specification), which is available via membership from: www.pcisig.com

The picture below illustrates the edge pin numbering. It starts on the right edge and alternates between top and bottom side. The removed pads in the keying notch counts (but as obviously non-existing).

M.2 Module Pin Numbering

The Wi-Fi interface uses either the SDIO, PCIe or the USB interface. The Bluetooth interface typically uses the UART interface for control and PCM interface for audio. The column "When is signal needed" indicates six different categories:

  • Always: These signals shall always be connected.
  • Wi-Fi SDIO: These signals shall always be connected when the Wi-Fi SDIO interface is used.
  • Wi-Fi PCIe: These signals shall always be connected when the Wi-Fi PCIe interface is used.
  • Wi-Fi USB: These signals shall always be connected then the Wi-Fi USB interface is used.
  • Bluetooth: These signals shall always be connected when the Bluetooth interface is used.
  • Bluetooth audio: These signals shall always be connected when the Bluetooth audio interface is used.
  • Optional: These signals are optional to connect, e.g., debug interfaces.

The table below lists the pin usage for a general M.2 module with E-keying and SDIO, PCIe or USB interface. Note that all M.2 modules do not support all features and do not connect all pins. See the specific M.2 module datasheet for details.

Note that the M.2 standard defines different voltage levels on different pins. Both 1.8V and 3.3V signaling is used.

Pin #Side of pcbM.2 NameVoltage Level and Signal DirectionWhen is signal neededNote
1TopGNDGNDAlwaysConnect to ground
2Bottom3.3 VAlwaysPower supply input. Connect to stable, low-noise 3.3V supply.

Current consumption depends on used M.2 module. Up to 3A might be needed for some MIMO Wi-Fi modules.
3TopUSB_D+-Wi-Fi USBConnected to USB interface of the module if it exists.
4Bottom3.3 VAlwaysPower supply input. Connect to stable, low-noise 3.3V supply.

Current consumption depends on used M.2 module. Up to 3A might be needed for some MIMO Wi-Fi modules.
5TopUSB_D-Wi-Fi USBConnected to USB interface of the module if it exists.
6BottomLED_1#OD output from M.2Currently not used but can be in the future.
7TopGNDGNDAlwaysConnect to ground
8BottomPCM_CLK1.8V I/OBluetooth audioFor Bluetooth audio interface: BT_PCM_CLK
9TopSDIO CLK1.8V Input to M.2Wi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_CLK
10BottomPCM_SYNC1.8V I/OBluetooth audioFor Bluetooth audio interface: BT_PCM_SYNC
11TopSDIO CMD1.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_CMD

Note: Require an external 10-50K ohm pullup
12BottomPCM_OUT1.8V output from M.2Bluetooth audioFor Bluetooth audio interface: BT_PCM_OUT
13TopSDIO DATA01.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_D0

Note: Require an external 10-50K ohm pullup
14BottomPCM_IN1.8V input to M.2Bluetooth audioFor Bluetooth audio interface: BT_PCM_IN
15TopSDIO DATA11.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_D1

Note: Require an external 10-50K ohm pullup
16BottomLED_2#OD output from M.2Currently not used but can be in the future.
17TopSDIO DATA21.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_D2

Note: Require an external 10-50K ohm pullup
18BottomGNDAlwaysConnect to ground
19TopSDIO DATA31.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_D3

Note: Require an external 10-50K ohm pullup
20BottomUART WAKE#3.3V OD output from M.2BluetoothFor Bluetooth UART interface: Signal from Bluetooth function to wake the host processor. Active low, i.e., wake when signal is low.

Named BT_HOST_WAKE_L or BT_WAKE_OUT, depending on wireless chipset.

Require an external 10K pullup resistor to 3.3V.
21TopSDIO WAKE#1.8V OD output from M.2Wi-Fi SDIOFor Wi-Fi SDIO interface: Signal from Wi-Fi function to wake the host processor. Active low, i.e., wake when signal is low.

Named WL_HOST_WAKE_L or WL_WAKE_OUT, depending on wireless chipset.

Require an external 10K pullup resistor to 1.8V.
22BottomUART TXD1.8V output from M.2BluetoothFor Bluetooth UART interface: BT_UART_TXD Connect to UART_RXD on target processor.
23TopSDIO RESET#1.8V input to M.2OptionalFor Wi-Fi SDIO interface: optional, independent reset of Wi-Fi interface. Active low.

Note that this is an optional signal is not used on all M.2 modules. Pin 56 (W_DISABLE1#) is often used to control the Wi-Fi interface but sometimes it controls all of the module, as a general power down signal, and then pin 23 (SDIO RESET#) is used for individual control of the Wi-Fi functionality.
24Key, non-existing
25Key, non-existing
26Key, non-existing
27Key, non-existing
28Key, non-existing
29Key, non-existing
30Key, non-existing
31Key, non-existing
32BottomUART_RXD1.8V input to M.2BluetoothFor Bluetooth UART interface: BT_UART_RXD

Connect to UART_TXD on target processor.
33TopGNDAlwaysConnect to ground
34BottomUART_RTS1.8V output from M.2BluetoothFor Bluetooth UART interface: BT_UART_RTS

Connect to UART_CTS on target processor and verify that this pin is actually an input on the target processor.
35TopPERp0PCIe data input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: transmit data from host processor
36BottomUART_CTS1.8V input to M.2BluetoothFor Bluetooth UART interface: BT_UART_CTS Connect to UART_RTS on target processor and verify that this pin is actually an output on the target processor.
37TopPERn0PCIe data input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: transmit data from host processor
38BottomVENDOR DEFINED1.8V I/OOptionalIf possible, the JTAG_TDO signal is connected to this pin
39TopGNDAlwaysConnect to ground
40BottomVENDOR DEFINED1.8V input to M.2Wi-Fi SDIOFor Wi-Fi SDIO interface: Signal from host processor to wake the Wi-Fi functionality. Active low, i.e., wake when signal is low.

Named WL_DEV_WAKE_L or WL_WAKE_IN, depending on wireless chipset.
41TopPETp0PCIe data output from M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: receive data to host processor
42BottomVENDOR DEFINED1.8V input to M.2BluetoothFor Bluetooth UART interface: Signal from host processor to wake the Bluetooth functionality. Active low, i.e., wake when signal is low.

Named BT_DEV_WAKE_L or BT_WAKE_IN, depending on wireless chipset.
43TopPETn0PCIe data output from M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: receive data to host processor
44BottomCOEX31.8V I/OOptionalIf possible, the JTAG_TDI signal is connected to this pin
45TopGNDAlwaysConnect to ground
46BottomCOEX_TXD1.8V I/OOptionalIf possible, the JTAG_TCK signal is connected to this pin
47TopREFCLKp0PCIe clock input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: 100MHz reference clock input
48BottomCOEX_RXD1.8V I/OOptionalIf possible, the JTAG_TMS signal is connected to this pin
49TopREFCLKn0PCIe clock input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: 100MHz reference clock input
50BottomSUSCLK3.3V input to M.2AlwaysExternal sleep clock input (32.768kHz)
51TopGNDAlwaysConnect to ground
52BottomPERST0#3.3V input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: Reset input signal, active low.
53TopCLKREQ0#3.3V OD output from M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: Clock request output from M.2

Require an external 10K pullup resistor to 3.3V.
54BottomW_DISABLE2#3.3V input to M.2BluetoothIndependent software reset of the Bluetooth functionality. This signal is sometimes called BT_REG_ON.

A high signal = Bluetooth enabled, a low signal = disabled.
55TopPEWAKE0#3.3V input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: Wakeup request from M.2

Require an external 10K pullup resistor to 3.3V.
56BottomW_DISABLE1#3.3V input to M.2AlwaysFull power control over module or independent software reset of the Wi-Fi functionality. This signal is sometimes called WL_REG_ON.

Some wireless chipsets have one common power control signal and then this signal controls the full power of the module, while some chipsets have independent Wi-Fi and Bluetooth power control and then this signal controls the Wi-Fi functionality of the module.

A high signal = Module/Wi-Fi enabled, a low signal = disabled.
57TopGNDAlwaysConnect to ground
58BottomI2C_SDA1.8V I/OI2C interface, data signal.

According to standard I2C interface implementation, this signal requires an external pullup resistor to 1.8V. Exact value depends on implementation. 1.5K-4.7K ohm is a common value.
59TopReserved1.8V I/O
60BottomI2C_CLK1.8V input to M.2I2C interface, clock signal.

According to standard I2C interface implementation, this signal requires an external pullup resistor to 1.8V. Exact value depends on implementation. 1.5K-4.7K ohm is a common value.
61TopReserved1.8V I/O
62BottomALERT#1.8V OD output from M.2OptionalOptional interrupt signal from wireless chipset.

Require an external 10K pullup resistor to 1.8V.
63TopGNDAlwaysConnect to ground
64BottomRESERVEDOn some M.2 modules from Embedded Artists, it is possible to apply a stable, low-noise, 3.3V / 100mA supply to this signal in order to get 3.3V voltage level on all signals.

Note that this is a nonfunction is non-standard, i.e., not part of the M.2 specification.
65TopReserved1.8V output from M.2
66BottomUIM_SWP1.8V I/OOptionalIn a previous pinning definition, this pin was defined as a signal from host processor to wake the Wi-Fi functionality. Active low, i.e., wake when signal is low.

Note that this functionality has moved to pin 40 instead.
67TopReserved1.8V input to M.2Optional
68BottomUIM_POWER_SNK1.8V I/O
69TopGNDAlwaysConnect to ground
70BottomUIM_POWER_SRC/GPIO_11.8V I/O
71TopReserved1.8V I/O
72Bottom3.3 VAlwaysPower supply input. Connect to stable, low-noise 3.3V supply.

Current consumption depends on used M.2 module. Up to 3A might be needed for some MIMO Wi-Fi modules.
73TopReserved1.8V I/O
74Bottom3.3 VAlwaysPower supply input. Connect to stable, low-noise 3.3V supply.

Current consumption depends on used M.2 module. Up to 3A might be needed for some MIMO Wi-Fi modules.
75TopGNDAlwaysConnect to ground

It can be difficult to get an overview of the table above. The tables below list the needed signals to implement based on which interfaces to implement.

Always Implement

The signals below should always be implemented/connected.

Pin #Side of pcbM.2 NameVoltage Level and Signal DirectionWhen is signal neededNote
1TopGNDGNDAlwaysConnect to ground
2Bottom3.3 VAlwaysPower supply input. Connect to stable, low-noise 3.3V supply.

Current consumption depends on used M.2 module. Up to 3A might be needed for some MIMO Wi-Fi modules.
4Bottom3.3 VAlwaysPower supply input. Connect to stable, low-noise 3.3V supply.

Current consumption depends on used M.2 module. Up to 3A might be needed for some MIMO Wi-Fi modules.
7TopGNDGNDAlwaysConnect to ground
18BottomGNDAlwaysConnect to ground
33TopGNDAlwaysConnect to ground
39TopGNDAlwaysConnect to ground
45TopGNDAlwaysConnect to ground
50BottomSUSCLK3.3V input to M.2AlwaysExternal sleep clock input (32.768kHz) that is used for low-power mode timing on many M.2 modules. Leave open or ground if no clock signal is provided.
51TopGNDAlwaysConnect to ground
56BottomW_DISABLE1#3.3V input to M.2AlwaysFull power control over module or independent software reset of the Wi-Fi functionality. This signal is sometimes called WL_REG_ON.

Some wireless chipsets have one common power control signal and then this signal controls the full power of the module, while some chipsets have independent Wi-Fi and Bluetooth power control and then this signal controls the Wi-Fi functionality of the module.

A high signal = Module/Wi-Fi enabled, a low signal = disabled.
57TopGNDAlwaysConnect to ground
63TopGNDAlwaysConnect to ground
69TopGNDAlwaysConnect to ground
72Bottom3.3 VAlwaysPower supply input. Connect to stable, low-noise 3.3V supply.

Current consumption depends on used M.2 module. Up to 3A might be needed for some MIMO Wi-Fi modules.
74Bottom3.3 VAlwaysPower supply input. Connect to stable, low-noise 3.3V supply.

Current consumption depends on used M.2 module. Up to 3A might be needed for some MIMO Wi-Fi modules.
75TopGNDAlwaysConnect to ground

Implement for Wi-Fi over SDIO

The signals below should always be implemented/connected to support Wi-Fi over SDIO

Pin #Side of pcbM.2 NameVoltage Level and Signal DirectionWhen is signal neededNote
9TopSDIO CLK1.8V Input to M.2Wi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_CLK
11TopSDIO CMD1.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_CMD

Note: Require an external 10-50K ohm pullup
13TopSDIO DATA01.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_D0

Note: Require an external 10-50K ohm pullup
15TopSDIO DATA11.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_D1

Note: Require an external 10-50K ohm pullup
17TopSDIO DATA21.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_D2

Note: Require an external 10-50K ohm pullup
19TopSDIO DATA31.8V I/OWi-Fi SDIOFor Wi-Fi SDIO interface: SDIO_D3

Note: Require an external 10-50K ohm pullup
21TopSDIO WAKE#1.8V OD output from M.2Wi-Fi SDIOFor Wi-Fi SDIO interface: Signal from Wi-Fi function to wake the host processor. Active low, i.e., wake when signal is low.

Named WL_HOST_WAKE_L or WL_WAKE_OUT, depending on wireless chipset.

Require an external 10K pullup resistor to 1.8V.
23TopSDIO RESET#1.8V input to M.2OptionalFor Wi-Fi SDIO interface: optional, independent reset of Wi-Fi interface. Active low.

Note that this is an optional signal is not used on all M.2 modules. Pin 56 (W_DISABLE1#) is often used to control the Wi-Fi interface but sometimes it controls all of the module, as a general power down signal, and then pin 23 (SDIO RESET#) is used for individual control of the Wi-Fi functionality.
40BottomVENDOR DEFINED1.8V input to M.2Wi-Fi SDIOFor Wi-Fi SDIO interface: Signal from host processor to wake the Wi-Fi functionality. Active low, i.e., wake when signal is low.

Named WL_DEV_WAKE_L or WL_WAKE_IN, depending on wireless chipset.

Implement for Wi-Fi over PCIe

The signals below should always be implemented/connected to support Wi-Fi over PCIe

Pin #Side of pcbM.2 NameVoltage Level and Signal DirectionWhen is signal neededNote
35TopPERp0PCIe data input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: transmit data from host processor
37TopPERn0PCIe data input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: transmit data from host processor
41TopPETp0PCIe data output from M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: receive data to host processor
43TopPETn0PCIe data output from M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: receive data to host processor
47TopREFCLKp0PCIe clock input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: 100MHz reference clock input
49TopREFCLKn0PCIe clock input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: 100MHz reference clock input
52BottomPERST0#3.3V input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: Reset input signal, active low.
53TopCLKREQ0#3.3V OD output from M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: Clock request output from M.2

Require an external 10K pullup resistor to 3.3V.
55TopPEWAKE0#3.3V input to M.2Wi-Fi PCIeFor Wi-Fi PCIe interface: Wakeup request from M.2

Require an external 10K pullup resistor to 3.3V.

Implement for Wi-Fi and/or Bluetooth over USB

The signals below should always be implemented/connected to support Wi-Fi and/or Bluetooth over USB.

Pin #Side of pcbM.2 NameVoltage Level and Signal DirectionWhen is signal neededNote
3TopUSB_D+-Wi-Fi USBConnected to USB interface of the module if it exists.
5TopUSB_D-Wi-Fi USBConnected to USB interface of the module if it exists.

Implement for Bluetooth over UART

The signals below should always be implemented/connected to support Bluetooth over UART.

Pin #Side of pcbM.2 NameVoltage Level and Signal DirectionWhen is signal neededNote
20BottomUART WAKE#3.3V OD output from M.2BluetoothFor Bluetooth UART interface: Signal from Bluetooth function to wake the host processor. Active low, i.e., wake when signal is low.

Named BT_HOST_WAKE_L or BT_WAKE_OUT, depending on wireless chipset.

Require an external 10K pullup resistor to 3.3V.
22BottomUART_TXD1.8V output from M.2BluetoothFor Bluetooth UART interface: BT_UART_TXD

Connect to UART_RXD on target processor.
32BottomUART_RXD1.8V input to M.2BluetoothFor Bluetooth UART interface: BT_UART_RXD

Connect to UART_TXD on target processor.
34BottomUART_RTS1.8V output from M.2BluetoothFor Bluetooth UART interface: BT_UART_RTS

Connect to UART_CTS on target processor and verify that this pin is actually an input on the target processor.
36BottomUART_CTS1.8V input to M.2BluetoothFor Bluetooth UART interface: BT_UART_CTS

Connect to UART_RTS on target processor and verify that this pin is actually an output on the target processor.
42BottomVENDOR DEFINED1.8V input to M.2BluetoothFor Bluetooth UART interface: Signal from host processor to wake the Bluetooth functionality. Active low, i.e., wake when signal is low.

Named BT_DEV_WAKE_L or BT_WAKE_IN, depending on wireless chipset.
54BottomW_DISABLE2#3.3V input to M.2BluetoothIndependent software reset of the Bluetooth functionality. This signal is sometimes called BT_REG_ON.

A high signal = Bluetooth enabled, a low signal = disabled.

Implement for Bluetooth Audio over PCM

The signals below should always be implemented/connected to support Bluetooth audio over PCM. It is assumed that the Bluetooth interface in general (over UART or USB) is also supported for this interface to be available.

Pin #Side of pcbM.2 NameVoltage Level and Signal DirectionWhen is signal neededNote
8BottomPCM_CLK1.8V I/OBluetooth audioFor Bluetooth audio interface: BT_PCM_CLK
10BottomPCM_SYNC1.8V I/OBluetooth audioFor Bluetooth audio interface: BT_PCM_SYNC
12BottomPCM_OUT1.8V output from M.2Bluetooth audioFor Bluetooth audio interface: BT_PCM_OUT
14BottomPCM_IN1.8V input to M.2Bluetooth audioFor Bluetooth audio interface: BT_PCM_IN

Optional Interfaces

The signals below can optionally be implemented to support a wider range of M.2 modules.

Pin #Side of pcbM.2 NameVoltage Level and Signal DirectionWhen is signal neededNote
6BottomLED_1#OD output from M.2Currently not used but can be in the future.
16BottomLED_2#OD output from M.2Currently not used but can be in the future.
58BottomI2C_SDA1.8V I/OI2C interface, data signal.

According to standard I2C interface implementation, this signal requires an external pullup resistor to 1.8V. Exact value depends on implementation. 1.5K-4.7K ohm is a common value.
60BottomI2C_CLK1.8V input to M.2I2C interface, clock signal.

According to standard I2C interface implementation, this signal requires an external pullup resistor to 1.8V. Exact value depends on implementation. 1.5K-4.7K ohm is a common value.
62BottomALERT#1.8V OD output from M.2OptionalOptional interrupt signal from wireless chipset.

Require an external 10K pullup resistor to 1.8V.
64BottomRESERVEDOn some M.2 modules from Embedded Artists, it is possible to apply a stable, low-noise, 3.3V / 100mA supply to this signal to get 3.3V voltage level on all signals.

Note that this is a nonfunction is non-standard, i.e., not part of the M.2 specification.
66BottomUIM_SWP1.8V I/OOptionalIn a previous pinning definition, this pin was defined as a signal from host processor to wake the Wi-Fi functionality. Active low, i.e., wake when signal is low.

Note that this functionality has moved to pin 40 instead.

M.2 Pin Definition Change

Based on initial experience with the M.2 pinning jointly defined by Embedded Artists, Murata, NXP and Infineon/Cypress a pinning change was decided.

The signal from the host processor to wake the Wi-Fi functionality (when the Wi-Fi SDIO interface is used) that was originally specified for pin 66 has been changed to pin 40. This is the signal named WL_DEV_WAKE_L or WL_WAKE_IN, depending on wireless chipset.

If backward compatibility is needed, just connect pin 40 and 66 (both via zero-ohm series resistors) of the M.2 connector.

All M.2 boards from Embedded Artists has transitioned to the new pinning definition, i.e., pin 40 is used for signal WL_DEV_WAKE_L / WL_WAKE_IN.

Wake-up Signals

There are four wake-up signals defined, two related to the Wi-Fi functionality and two for the Bluetooth functionality. Note that all M.2 modules do not support all four signals. Some support all of them. Some support only one or two of them. It is the firmware that is downloaded after power-up that implement the wake-up signals and support for these signals can also differ between firmware versions.

  • M.2 module-to-host wake-up for Wi-Fi interface, M.2 pin 21. The signal is referred to as WL_WAKE_OUT or WL_HOST_WAKE_L, depending on different chipsets, and is an output from the M.2 module. The signal is used to exit the host processor from any sleep mode. The signal is active low:

    • Low/Asserted: Host device must wake-up or remain awake
    • High/De-asserted: Host device can sleep when the sleep criteria is met.
  • Host processor-to-M.2 module wake-up for Wi-Fi interface, M.2 pin 40. The signal is referred to as WL_WAKE_IN or WL_DEV_WAKE_L, depending on different chipsets, and is an input to the M.2 module. The signal is used to exit Wi-Fi sleep/low-power modes. The signal is active low:

    • Low/Asserted: Wi-Fi interface must wake-up or remain awake
    • High/De-asserted: Wi-Fi interface can enter sleep or low-power mode when the criteria is met.
  • M.2 module-to-host wake-up for Bluetooth interface, M.2 pin 20. The signal is referred to as BT_WAKE_OUT or BT_HOST_WAKE_L, depending on different chipsets, and is an output from the M.2 module. The signal is used to exit the host processor from any sleep mode. The signal is active low:

    • Low/Asserted: Host device must wake-up or remain awake
    • High/De-asserted: Host device can sleep when the sleep criteria is met.
  • Host processor-to-M.2 module wake-up for Bluetooth interface, M.2 pin 42. The signal is referred to as BT_WAKE_IN or BT_DEV_WAKE_L, depending on different chipsets, and is an input to the M.2 module. The signal is used to exit Wi-Fi sleep/low-power modes. The signal is active low:

    • Low/Asserted: Bluetooth interface must wake-up or remain awake
    • High/De-asserted: Bluetooth interface can enter sleep or low-power mode when the criteria is met.

It is recommended to implement all the signals, even if the currently used M.2 module does not support all signals, since the M.2 interface will be compatible with more M.2 modules. It also allows for future upgrade of functionality around sleep and low-power modes.

VDDIO Override Feature

The M.2 standard specify 1.8V logic level on several of the data and control signals. On some M.2 boards, it is possible to override the voltage level for the 1.8V signals via pin 64. Apply a 3.3V / 100 mA supply to pin 64 to get 3.3V voltage level on all data and control signals.

Check the specific M.2 datasheet for details if this non-M.2 standard functionality is supported, or not. Some M.2 boards support the 3.3V signaling only after a small rework. Also check the specific M.2 datasheet for details.

Note: If 3.3V signaling level is used, the SDIO clock frequency is limited to 50 MHz. This can limit the data throughput of the Wi-Fi interface.

SDIO Interface

The SDIO interface conforms to the SDIO v3.0 specification, including the UHS-I modes, and is backward compatible with SDIO v2.0.

SDIO bus speed modesMax SDIO clock frequencyMax bus speedSignaling voltage according to M.2 specificationSupported in 3.3V VDDIO Override Mode
DS (Default speed)25 MHz12.5 MByte/s1.8 VYes
HS (High speed)50 MHz25 MByte/s1.8 VYes
SDR1225 MHz12.5 MByte/s1.8 VNo
SDR2550 MHz25 MByte/s1.8 VNo
SDR50100 MHz50 MByte/s1.8 VNo
SDR104208 MHz104 MByte/s1.8 VNo
DDR5050 MHz50 MByte/s1.8 VNo

Note: the SDIO voltage level is 1.8V, as specified in the M.2 standard. It is not allowed to start at 3.3V and then switch to 1.8V signaling (as is normally done for an SD card interface). The signaling voltage level should be fixed at 1.8V.

Tri-band Radio Support

NXP have defined a tri-band chipset, supporting Wi-Fi, Bluetooth and 802.15.4. The 802.15.4 support is enabled via the I2C interface and when enabled, a non-M.2 standard SPI interface is available as interface to the functionality. As of March 2022, 2EL M.2 and 2ER M.2 modules support the tri-band radio. NXP’s specification of the Tri-band M.2 interface can be found in document AN13049.

M.2 PinPin nameTri-band definitionStandard definition
38VENDOR DEFINEDSPI_TXD: SPI transmit signal.
40VENDOR DEFINEDSPI_RXD: SPI receive signal.WL_WAKE_IN
42VENDOR DEFINEDSPI_CLK: SPI clock signal.BT_WAKE_IN
58I2C_DATAI2C SDA must be implemented.I2C SDA is optional
60I2C_CLKI2C SDA must be implemented.I2C_CLK is optional
62ALERT#SPI_INT: SPI interrupt signal. Open drain. Pullup required on platform.Is optional
64RESERVEDSPI_FRM: SPI select signal.Optional VDDIO override. For compatibility with Tri-band functionality, do not implement the VDDIO override functionality.

When 802.15.4 is enabled, the WL_WAKE_IN and BT_WAKE_IN signals are generated via the I2C GPIO expander on the M.2 module.

High Speed UART Interface

The M.2 standard define a high-speed Universal Asynchronous Receiver/Transmitter (UART), supporting the Bluetooth interface. Beside transporting the HCI Bluetooth data, the UART channel is also used for downloading the Bluetooth firmware to the chipset.

In order not to limit the data throughput over the Bluetooth interface, the UART typically supports standard baud rates up to 4 Mbit/s. The common default bit rate after reset is 3000000 bps but it can differ between M.2 modules.

The UART interface settings are: 8 data bits, no parity, 1 stop bit (i.e., 8N1), RTS/CTS flow control, and follows the industry standard 16550 specification.

Note: Due to the high bit rate UART RTS/CTS (hardware) flow control is not optional, it is mandatory. RTS/CTS flow control prevents temporary UART FIFO-buffer overruns. The HCI protocol implements its own, software controlled, flow control.

The table below lists how to connect the UART data and flow control signals.

M.2 Pin #M.2 Name and signal directionInterface on host side
22UART_TXD, output from the M.2 moduleConnect to Host UART_RXD (input on host processor)
32UART_RXD, input to the M.2 moduleConnect to Host UART_TXD (output from host processor)
34UART_RTS, output from the M.2 moduleConnect to Host UART_CTS (input on host processor) Received signal high: Host can send data Received signal low: Host is not allowed to send data
36UART_CTS, input to the M.2 moduleConnect to Host UART_RTS (output from host processor) Signal high: chipset can send data Signal low: chipset is not allowed to send data (because the receive FIFO-buffer is temporary full)

Although UART is the most common interface to Bluetooth, some M.2 modules support other interfaces, like SDIO or PCIe.